1. Technical Field of the Invention
The present invention relates to an output buffer.
More specifically, the invention relates to an output buffer of the type comprising at least a first and a second stage, formed by respective first transistors and second transistors inserted, in series with each other, between a first and a second voltage reference and having common conduction terminals connected to an output terminal of said output buffer, having in turn an input terminal connected to control terminals of said transistors of said first stage through an open loop driving circuit.
The invention also relates to a current detector of an electronic device portion.
2. Description of Related Art
As is well known, output buffers play a more and more important role in reaching the requested performances of integrated devices.
The characteristics with which these buffers are designed in fact determine the times necessary for switching of an outputting datum and the so called drivable maximum capacitive fan out of the device.
On the other hand, the increase of the operation frequencies of integrated devices implies that the interconnections have no more negligible lengths and the propagation times can be compared to those ones peculiar to data switchings, making it necessary to consider the problems linked to the reflections and complicating the output buffer designs.
In particular, if the switches of digital signals transmitted on an interconnection are to be optimized (and thus their switching times are to be minimized) it is necessary to design output buffers able to realize an impedance adaptation.
Moreover, due to the non-ideality of the supply interconnections ground bounce phenomena can occur linked to the quickness with which these buffers are able to supply current.
All the considerations made highlight the importance of optimized solutions for output buffers.
To understand the problems involved, it is suitable to simplify the analysis of an output buffer by means of a model comprising the necessary interconnections, which cannot be considered ideal any more.
In its essential form, an integrated device output buffer can, in a first approximation, be patterned as a voltage generator having, in series, an equivalent resistance. This latter parameter represents the buffer output impedance during a transient.
By using for example the conditions expressed by Sanjay Dabral and Timothy J. Maloney in the article entitled: “Basic ESD and I/O design”, ed. Wiley Interscience, the disclosure of which is hereby incorporated by reference, and thus considering track lengths being much lower than a minimum value 1 min, the interconnection between a buffer and a load can be treated as a network with concentrated parameters R L C, where C is a load capacity, R is the resistance of a track and L its inductance.
It is suitable to remark that the above indicated simplifications however lead to obtaining valid results which are extendible also in the most general case of tracks which do not meet the previously expressed condition.
It is immediate to verify that, during a transition of a datum in the buffer, a reduction of the equivalent resistance implies: a decrease of the datum transition time (indicated as t10-90); a shift of the poles from real to complex conjugated of the transfer function of the buffer; an increase of the imaginary part of these poles; a decrease of the buffer damping factor; and an increase of the over and under elongations of a voltage signal at an output terminal of the buffer.
The main consequence of this behavior is an excessive supply and/or absorption, by the buffer, of current being useless to the datum transition purposes.
It is also theoretically possible that the oscillation of the output voltage signal causes an equivocalness of the datum transmitted by the buffer if it is higher than a logic threshold value.
The above cited phenomena take an increasing importance as the frequencies increase. To ensure shorter and shorter switching times for an output buffer it is thus substantially necessary to increase the current supplied by the buffer itself and thus reduce its equivalent output resistance.
Also the increase of the parasite elements (L C) being both on the output line and on the supply reference implies the accentuation of the oscillatory phenomena of the output voltage signal.
On the contrary an increase of the equivalent resistance during a transition implies: an increase of the datum transition time (indicated with t10-90); an increase of the buffer damping factor; and a decrease and, under suitable conditions (real poles), elimination of the over and under elongations of the buffer output voltage signal.
In other words, to optimize the electric performances of the buffer, it is necessary to minimize the datum transition time and to eliminate the over/under elongations of its output voltage signal.
A behavior of this kind can be obtained by varying the output resistance of the buffer itself. In particular, at the beginning of the transition the impedance must be maintained as small as possible so as to supply the maximum current being the voltage the same, while at the end of the transient the buffer must have such an impedance as to dampen the oscillations.
Different circuit solutions are known to obtain the above indicated “ideal” behavior.
In particular, circuit architectures are proposed which, by means of a feedback control loop, control the impedance of the output buffer thus limiting the oscillations both on the supply references and on the output terminals.
Examples of buffers realized by using such a feedback control loop are described for example in the following articles (the disclosures of which are incorporated by reference): Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu and Tin-Hao Lin, “Low switching noise and load-adaptative output buffer design techniques”, IEEE J. Solid-State Circuits, vol. 36, no. 8, August 2001, pp. 1239-1249; L. Carro and L. J. Bego, “Low ringing I/O buffer design”, Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Volume 2, May 31-Jun. 3, 1998 pp. 57-60 vol. 2; and E. Chioffi, F. Maloberti, G. Marchesi and G. Torelli, “High-speed, low-switching noise CMOS memory data output buffer”, IEEE J. Solid-State Circuits, vol. 29, no. 11, November 1994, pp. 1359-1365.
An operation scheme of an output buffer 1 realized by using a feedback control loop, such as in the above cited documents, is schematically shown in FIG. 1.
In particular, the output buffer 1 has an input terminal DATA receiving a datum to be transmitted and an output terminal PAD whereon there is a transmitted datum. The output buffer 1 comprises a final stage formed by a first and a second transistor T1, T2, inserted, in series with each other, between a first and a second voltage reference, in particular, the supply voltage reference Vcc and the ground GND.
The transistors T1 and T2 are MOS transistors, respectively of the P and N type, having respective gate terminals connected to a first and a second output terminal of a block 2 comprising, in a known way, a combinatory logic and a pre-buffer. The transistors T1 and T2 are also connected, in correspondence with the common drain terminals, to the output terminal PAD of the output buffer 1.
Finally, the block 2 has a first input terminal connected to the input terminal DATA of the output buffer 1 as well as a second input terminal feedback connected to the output terminal PAD of the output buffer 1, thus creating the desired feedback control loop, indicated with 3.
In particular, thanks to the circuit configuration shown, the output voltage Vpad of the buffer (voltage on the output terminal PAD, also simply called pad voltage) is squared with one or more inverted and compared, through several logic gates, with a signal at the input terminal DATA to establish where exactly in the transient the output buffer 1 is located. Thanks to this information, the impedance of the output buffer 1 and consequently its capacity of supplying current are thus regulated, this regulation being performed by the block 2.
Architectures of this kind are efficient until the signal measured has a monotonous progress, so that the switching threshold is crossed by the transition only once.
This condition however fails when the frequencies at issue make sure that the effects of the reflections on the load make the measured voltage non monotonous.
By using a patterning scheme of the output buffer 1, of its supply network 4 and of a load 5 connected thereto as shown in FIG. 2 (being Ra=0.1 W, La=2 nH, Z0=70 W, Td=0.2 ns and Cload=30 pF) it is possible to perform a simulation of a transient. The progresses are thus obtained of the output voltage signals Vpad on the terminal PAD and Vload on the load shown in FIG. 3 during a transition 0->1.
It is clear that an output voltage signal Vpad having the progress shown in FIG. 3 cannot be efficiently used in a control system as previously said.
In fact, if the load is of capacitive nature, and therefore if it behaves as a short circuit on the front of the datum to be transmitted, the output buffer 1 must have the opportunity to react with the maximum power at the reflection arrival. If the feedback control loop 3 acts by means of a comparison between the output voltage Vpad and a threshold, as in the prior art described in the above cited articles, then an output voltage signal Vpad as the one shown in FIG. 3 (corresponding to a real situation) could cause an anticipated increase of the output impedance with subsequent reduction of the current supplied by the output buffer 1. This implies an increase of the times peculiar of the data switching.
Moreover, since the feedback control loop 3 has an intrinsic delay, a situation in which the output buffer 1 operates exactly in opposition of phase with respect to what provided under “ideal” conditions could theoretically occur. In so doing dangerous oscillations of the output voltage signal Vpad could be triggered.
To overcome the problem of the sensitivity to the non monotony of the output voltage Vpad during the transient, the use is also known of a circuit 6 with hysteresis as a feedback element of the feedback control loop 3, as schematically shown in FIG. 4 and as described for example in above cited the article by Shyh-Jye Jou et al.
The introduction of such a circuit 6 with hysteresis is however substantially inefficient. In fact, to obtain a control which is non-sensitive to possible oscillations of the output voltage Vpad on the terminal PAD it is necessary to make the hysteresis cycle of the circuit 6 wide, the circuit thus reacting late and not bringing any benefit.
In particular, making reference to the progress of the output voltage Vpad on the terminal PAD shown in FIG. 3, it can be immediately deduced that the hysteresis cycle of the circuit 6 with hysteresis should be so wide as not to consider as significant the peak of 1.4V which occurs with time 3 ns. Consequently the circuit 6 with hysteresis could be triggered only with time 5 ns when the output voltage Vpad on the terminal PAD have exceeded 1.4V; in this case, however, the level of the voltage Vload on the capacitive load is by this time at a level corresponding to the high supply reference (+1.8V). Such a late intervention could not bring significant improvements of the over-elongations of the output voltage signal Vload.
In substance, the output buffers realized according to the prior art have the problem of the over/under elongations of the voltage signal Vload on a load connected thereto, essentially due to the parasite elements linked to the interconnections between the output terminal and the load and the proposed solutions using a feedback in voltage are inefficient since the voltage signal Vpad is irregular.
There is accordingly a need in the art for providing an output buffer able to reduce the over/under elongations of its output voltage signal optimizing in this way the transition time of the output terminal itself and overcoming the limits and drawbacks still affecting the buffers realized according to the prior art.